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this datasheet contains new product information. myson technology reserves the rights to modify the product specification witho ut notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sales of the product. revision 1.0 1/18 28/april/2000 MTV130 myson technology features general description block diagram ? horizontal sync input up to 150 khz. ? acceptable wide-range pixel clock up to 150 mhz. ? full screen self-test pattern generator. ? full-screen display consists of 15 (rows) by 30 (columns) characters. ? two font size 12x16 or 12x18 dot matrix per character. ? true totally 512 mask rom fonts including 496 standard fonts and 16 multi-color fonts. ? 8 color selection maximum per display character. ? double character height and/or width control. ? programmable positioning for display screen center. ? character bordering, shadowing and blinking effect. ? programmable character height (18 to 71 lines) control. ? row to row spacing control to avoid expansion distortion. ? 4 programmable windows with multi-level operation. ? shadowing on windows with programmable shadow width/height/color. ? software clears bit for full-screen erasing. ? intensity and fast blanking output. ? fade-in/fade-out or blending-in/blending-out effects. ? 4-channel/8-bit pwm d/a converter output. ? compatible with spi bus or i 2 c interface with slave address 7ah (slave address is mask option). ? 16-pin or 20-pin pdip/sop package. on-screen display for lcd monitor MTV130 is designed for lcd monitor applications to display built-in characters or fonts onto an lcd monitor screens. the display operation occurs by transferring data and control information from the micro-controller to ram through a serial data interface. it can execute full-screen display automatically, as well as specific functions such as character background, bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and row- to-row spacing, horizontal display resolution, full-screen erasing, fade-in/fade-out effect, windowing effect, shadow- ing on window and full-screen self-test pattern generator. MTV130 provides true 512 fonts including 496 standard fonts and 16 multi-color fonts and 2 font sizes, 12x16 or 12x18 for more efficacious applications. so each one of the 512 fonts can be displayed at the same time. the full osd menu is formed by 15 rows x 30 columns, which can be positioned anywhere on the monitor screen by changing vertical or horizontal delay. serial data interface address bus administrator vertical display control display & row control registers color encoder windows & frame control wr wg wb fbkgc blank lumar lumag lumab blink vclkx data vertd hord ch 8 8 7 bsen shadow osdenb hsp vsp horizontal display control clock generator 8 data lpn cws vclks 5 data cws chs 8 lumar lumag lumab blink craddr 8 luma border arwdb hdren vclkx hord 8 ch chs vertd 7 8 lpn nrow vdren 5 rcaddr daddr fontaddr winaddr pwmaddr 5 9 9 5 5 arwdb hdren vdren nrow data row, col ack 8 9 character rom user font ram luminance & bordger generator vdd vss vdda vssa rout gout bout fbkg htone hflb nc xin vflb ssb sck sda vsp hsp pwm d/a converter pwm0 pwm1 pwm2 pwm3 8 data 8 power on reset prb
revision 1.0 2/18 28/april/2000 MTV130 myson technology 1.0 pin connection 2.0 pin descriptions name i/o pin no. descriptions p16 p20 vss - 1 1 ground. this ground pin is used to internal circuitry. xin i 2 2 pixel clock input. this is a clock input pin. MTV130 is driven by an external pixel clock source for all the logics inside. the frequency of xin must be the integral time of pin hflb. nc i 3 3 no connection. vdd - 4 4 power supply. positive 5 v dc supply for internal circuitry. and a 0.1uf decoupling capacitor should be connected across to vdd and vss. hflb i 5 5 horizontal input. this pin is used to input the horizontal synchronizing signal. it is a leading edge triggered and has an internal pull-up resistor. ssb i 6 6 serial interface enable. it is used to enable the serial data and is also used to select the operation of i 2 c or spi bus. if this pin is left floating, i 2 c bus is enabled, otherwise the spi bus is enabled. sda i 7 7 serial data input. the external data transfer through this pin to internal display registers and control registers. it has an internal pull-up resistor. sck i 8 8 serial clock input. the clock-input pin is used to synchronize the data transfer. it has an internal pull-up resistor. pwm0 o - 9 open-drain pwm d/a converter 0. the output pulse width is program- mable by the register of row 15, column 23. pwm1 o - 10 open-drain pwm d/a converter 1. the output pulse width is program- mable by the register of row 15, column 24. pwm2 o - 11 open-drain pwm d/a converter 2. the output pulse width is program- mable by the register of row 15, column 25. pwm3 o - 12 open-drain pwm d/a converter 3. the output pulse width is program- mable by the register of row 15, column 26. vss xin nc vdd hflb ssb sda sck vss rout gout bout fbkg int vflb vdd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 m t v 1 3 0 p - x x vss xin nc vdd hflb ssb sda sck pwm0 pwm1 vss rout gout bout fbkg int vflb vdd pwm3 pwm2 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 m t v 1 3 0 p 2 0 - x x
revision 1.0 3/18 28/april/2000 MTV130 myson technology 3.0 functional descriptions 3.1 serial data interface the serial data interface receives data transmitted from an external controller. and there are 2 types of bus can be accessed through the serial data interface, one is spi bus and other is i 2 c bus. 3.1.1 spi bus while ssb pin is pulled to "high" or "low" level, the spi bus operation is selected. and a valid transmission should be starting from pulling ssb to "low" level, enabling MTV130 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. the protocol is shown in figure 1. there are three transmission formats shown as below: format (a) r - c - d ? r - c - d ? r - c - d ..... format (b) r - c - d ? c - d ? c - d ? c - d ..... format (c) r - c - d ? d ? d ? d ? d ? d ..... where r=row address, c=column address, d=display data 3.1.2 i 2 c bus i 2 c bus operation is only selected when ssb pin is left floating. and a valid transmission should be starting from writing the slave address 7ah to MTV130. the protocol is shown in figure 2. vdd - 9 13 power supply. positive 5 v dc supply for internal circuitry and a 0.1uf decoupling capacitor should be connected across to vdd and vss. vflb i 10 14 vertical input. this pin is used to input the vertical synchronizing signal. it is leading triggered and has an internal pull-up resistor. int o 11 15 intensity color output. 16-color selection is achievable by combining this intensity pin with r/g/b output pins. fbkg o 12 16 fast blanking output. it is used to cut off external r, g, b signals of vga while this chip is displaying characters or windows. bout o 13 17 blue color output. it is a blue color video signal output. gout o 14 18 green color output. it is a green color video signal output. rout o 15 19 red color output. it is a red color video signal output. vss - 16 20 ground. this ground pin is used to internal circuitry. name i/o pin no. descriptions p16 p20 ms b lsb ssb sck sda first byte last byte figure 1. data transmission protocol (spi)
revision 1.0 4/18 28/april/2000 MTV130 myson technology there are three transmission formats shown as below: format (a) s - r - c - d ? r - c - d ? r - c - d ..... format (b) s - r - c - d ? c - d ? c - d ? c - d ..... format (c) s - r - c - d ? d ? d ? d ? d ? d ..... where s=slave address, r=row address, c=column address, d=display data each arbitrary length of data packet consists of 3 portions viz, row address (r), column address (c), and display data (d). format (a) is suitable for updating small amount of data which will be allocated with different row address and column address. format (b) is recommended for updating data that has same row address but different column address. massive data updating or full screen data change should use format (c) to increase transmission efficiency. the row and column address will be incremented automatically when the for- mat (c) is applied. furthermore, the undefined locations in display or fonts ram should be filled with dummy data. there are 2 types of data should be accessed through the serial data interface, one is address bytes of dis- play registers, and other is attribute bytes of display registers, the protocol are same for all except the bit5 of row address and the bit5 of column address. the msb(b7) is used to distinguish row and column addresses when transferring data from external controller. the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. bit5 of row address for display register is used to distinguish address byte when it is set to "0" and attribute byte when it is set to "1". and at address bytes, bit5 of column address is the msb (bit8) and data bytes are the 8 lsb (bit7~bit0) of dis- play fonts address to save half mcu memory for true 512 fonts. so each one of the 512 fonts can be dis- played at the same time. see table 1. and for format (c), since d8 is filled while program column address of address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program column address of address bytes again. the data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a) and (c), but not from format (c) back to format (a) and (b). the alternation between transmission formats is configured as the state diagram shown in figure 3. table 1. the configuration of transmission formats. address b7 b6 b5 b4 b3 b2 b1 b0 format address bytes of display reg. row 1 0 0 x r3 r2 r1 r0 a,b,c column ab 0 0 d8 c4 c3 c2 c1 c0 a,b column c 0 1 d8 c4 c3 c2 c1 c0 c data d7 d6 d5 d4 d3 d2 d1 d0 a,b,c attribute bytes of display reg. row 1 0 1 r4 r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c data d7 d6 d5 d4 d3 d2 d1 d0 a,b,c figure 2. data transmission protocol (i 2 c) sck sda start ack second byte last byte ack stop b7 b6 b0 b7 b0 first byte
revision 1.0 5/18 28/april/2000 MTV130 myson technology 3.2 address bus administrator the administrator manages bus address arbitration of internal registers or user fonts ram during external data write in. the external data write through serial data interface to registers must be synchronized by inter- nal display timing. in addition, the administrator also provides automatic increment to address bus when exter- nal write using format (c). 3.3 vertical display control the vertical display control can generates different vertical display sizes for most display standards in current monitors. the vertical display size is calculated with the information of double character height bit(chs), verti- cal display height control register(ch6-ch0).the algorithm of repeating character line display are shown as table 2 and table 3. the programmable vertical size range is 270 lines to maximum 2130 lines. the vertical display center for full screen display could be figured out according to the information of vertical starting position register (vertd) and vflb input. the vertical delay starting from the leading edge of vflb, is calculated with the following equation: vertical delay time = ( vertd * 4 + 1 ) * h where h = one horizontal line display time table 2. repeat line weight of character ch6 - ch0 repeat line weight ch6,ch5=11 +18*3 ch6,ch5=10 +18*2 ch6,ch5=0x +18 ch4=1 +16 ch3=1 +8 ch2=1 +4 ch1=1 +2 ch0=1 +1 initiate row col c col ab da c da ab 1, x 0, 1 0, 0 x, x x, x 0, 1 1, x 1, x format (a) format (b) format (c) x, x 0, x input = b7, b6 0, 0 figure 3. transmission state diagram
revision 1.0 6/18 28/april/2000 MTV130 myson technology note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be repeated. 3.4 horizontal display control the horizontal display control is used to generate control timing for horizontal display based on double char- acter width bit (cws), horizontal positioning register (hord) and hflb input. a horizontal display line includes 360 dots for 30 display characters and the remaining dots for blank region. the horizontal delay starting from hflb leading edge is calculated with the following equation, horizontal delay time = ( hord * 6 + 49) * p where p = 1 xin pixel display time 3.5 display & row control registers the internal ram contains display and row control registers. the display registers have 450 locations which are allocated between (row 0, column 0) to (row 14, column 29), as shown in figure 4 and figure 5. each dis- play register has its corresponding character address on address byte, its corresponding background color, 1 blink bit and its corresponding color bits on attribute bytes. the row control register is allocated at col- umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. if double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden. figure 4. address bytes of display registers memory map table 3. repeat line number of character repeat line weight repeat line # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 - - - - - - - - v - - - - - - - - - +2 - - - - v - - - - - - - v - - - - - +4 - - v - - - v - - - v - - - v - - - +8 - v - v - v - v - v - v - v - v - - +16 - v v v v v v v v v v v v v v v v - +17 v v v v v v v v v v v v v v v v v - +18 v v v v v v v v v v v v v v v v v v row # column # 0 1 28 29 3 0 31 0 1 13 14 character address bytes of display registers row attribute crtl reg r e s e r v e d
revision 1.0 7/18 28/april/2000 MTV130 myson technology figure 5. attribute bytes of display registers memory map address bytes: address registers, craddr - define rom character address from address 0 to 511. row control registers, (row 0 - 14) chs - define double height character to the respective row. cws - define double width character to the respective row. attribute bytes: bgr, bgg, bgb - these three bits define the color of the background for its relative address character. if all three bits are clear, no background will be shown(transparent). therefore, total 7 back- ground color can be selected. row # column # 0 1 28 29 30 31 0 1 13 14 character attribute bytes of display registers reserved row 15 column# 0 11 12 22 23 27 28 31 window1 ~ window4 frame crtl reg pwm d/a crtl reg reserved row 16 column# 0 1 2 31 window shadow color reserved b8 b7 b6 b5 b4 b3 b2 b1 b0 craddr msb lsb coln 30 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - chs cws b7 b6 b5 b4 b3 b2 b1 b0 - bgr bgg bgb blink r g b
revision 1.0 8/18 28/april/2000 MTV130 myson technology blink - enable blinking effect while this bit is set to " 1 ". and the blinking is alternate per 32 vertical frames. r, g, b - these three bits are used to specify its relative address character color. 3.6 character rom MTV130 character rom contains 512 built-in characters and symbols including 496 standard fonts and 16 multi-color fonts. the 496 standard fonts are located from address 0 to 495. and the 16 multi-color fonts are located from address 496 to 511. each character and symbol consists of 12x18 dots matrix. the detail pattern structures for each character and symbols are shown in ? characters and symbols pattern ? on page 18. 3.7 multi-color font the color fonts comprises three different r, g, b fonts. when the code of color font is accessed, the separate r/g/b dot pattern is output to corresponding r/g/b output. see figure 6 for the sample displayed color font. note: no black color can defined in color font, black window underline the color font can make the dots become black in color. the detail pattern structures for each character and symbols are shown in ? charac- ters and symbols pattern ? on page 18. table 4. the multi-color font color selection 3.8 luminance & border generator there are 3 shift registers included in the design which can shift out of luminance and border dots to color encoder. the bordering and shadowing feature is configured in this block. for bordering effect, the character will be enveloped with blackedge on four sides. for shadowing effect, the character is enveloped with blackedge for right and bottom sides only. r g b background color 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magent 1 0 1 yellow 1 1 0 white 1 1 1 r g b magent green cyan blue figure 6. example of multi-color font
revision 1.0 9/18 28/april/2000 MTV130 myson technology 3.9 window and frame control the display frame position is completely controlled by the contents of vertd and hord. the window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in figure 5 . window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. more detailed infor- mation is described as follows: 1. window control registers, row 15 start(end) addr - these addresses are used to specify the window size. it should be noted that when the start address is greater than the end address, the window will be disabled. wen - enable the relative background window display. wshd - enable shadowing on the window. r, g, b - specify the color of the relative background window. 2. frame control registers, row 15 vertd - specify the starting position for vertical display. the total steps are 256, and the increment of each step is 4 horizontal display lines. the initial value is 4 after power up. hord - define the starting position for horizontal display. the total steps are 256, and the increment of each step is 6 dots. the initial value is 15 after power up. ch6-ch0 - define the character vertical height, the height is programmable from 18 to 71 lines. the character vertical height is at least 18 lines if the contents of ch6-ch0 is less than 18. for example, when the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. and if the con- column 0,3,6,or 9 b7 b6 b5 b4 b3 b2 b1 b0 row start addr msb lsb row end addr msb lsb column 1,4,7,or 10 b7 b6 b5 b4 b3 b2 b1 b0 col start addr msb lsb wen - wshd column 2,5,8,or 11 b7 b6 b5 b4 b3 b2 b1 b0 col end addr msb lsb r g b column 12 b7 b6 b5 b4 b3 b2 b1 b0 vertd msb lsb column 13 b7 b6 b5 b4 b3 b2 b1 b0 hord msb lsb column 14 b7 b6 b5 b4 b3 b2 b1 b0 - ch6 ch5 ch4 ch3 ch2 ch1 ch0
revision 1.0 10/18 28/april/2000 MTV130 myson technology tents of ch4-ch0 is greater than or equal to 18, it will be regarded as equal to 17. see table 2 and table 3 for detail description of this operation. this byte is reserved for internal testing. rspace - define the row to row spacing in unit of horizontal line. that is, extra rspace horizontal lines will be appended below each display row, and the maximum space is 31 lines. the initial value is 0 after power up. osden - activate the osd operation when this bit is set to "1". the initial value is 0 after power up. bsen - enable the bordering and shadowing effect. shadow - bordering and shadowing effect select bit. activate the shadowing effect if this bit is set, otherwise the bordering is chosen. fben - enable the fade-in/fade-out and blending-in/blending-out effect when osd is turned on from off state or vice verca. blend - fade-in/fade-out and blending-in/blending-out effect select bit. activate the blendinf-in/blending-out function if this bit is set, otherwise the fade-in/fade-out function is chosen. these function roughly takes about 0.5 second to fully display the whole menu or to disappear completely. wenclr - clear all wen bits of window control registers when this bit is set to "1". the initial value is 0 after power up. ramclr - clear all address bytes, bgr, bgg, bgb and blink bits of display registers when this bit is set to "1". the initial value is 0 after power up. fbkgc - define the output configuration for fbkg pin. when it is set to "0", the fbkg outputs high during the displaying of characters or windows, otherwise, it outputs high only during the displaying of charac- ter. tric - define the driving state of output pins rout, gout, bout and fbkg when osd is disabled. that is, while osd is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are in high impedance state. the initial value is 0 after power up. fss - font size selection. = 1 t 12x18 font size selected. = 0 t 12x16 font size selected. column 15 b7 b6 b5 b4 b3 b2 b1 b0 reserved column 16 b7 b6 b5 b4 b3 b2 b1 b0 - - - rspace msb lsb column 17 b7 b6 b5 b4 b3 b2 b1 b0 osden bsen shadow fben blend wenclr ramclr fbkgc column 18 b7 b6 b5 b4 b3 b2 b1 b0 tric fss - dwe hsp vsp pwm1 pwm0
revision 1.0 11/18 28/april/2000 MTV130 myson technology dwe - enable double width. when the bit is set to ?1?, the display of osd menu can change to half resolution for double character width, and then the number of pixels of each line should be even. the initial value is 0 after power up. hsp - = 1 t accept positive polarity hsync input. = 0 t accept negative polarity hsync input. vsp - = 1 t accept positive polarity vsync input. = 0 t accept negative polarity vsync input. pwm1, pwm0 - select the pwmck output frequency. = (0, 0) t xin frequency /8 = (0, 1) t xin frequency /4 = (1, 0) t xin frequency /2 = (1, 1) t xin frequency /1 the initial value is (0, 0) after power up. notes : when xin is not present, don?t write data in any address. if data is written in any other address, a malfunction may occur. csr, csg, csb - define the color of bordering or shadowing on characters. the initial value is (0, 0, 0) after power up. fsw - enable full screen self-test pattern and force the fbkg pin output to high to disable video rgb while this bit is set to "1". the self-test pattern?s color is determined by (fsr, fsg, fsb) bits. table 5. pwmck frequency and pwmda sampling rate (pwm1, pwm0) pwmck freq pwmda sampling rate ( 0, 0 ) xin frequency /8 xin frequency /(8 * 256) ( 0, 1 ) xin frequency /4 xin frequency /(4 * 256) ( 1, 0 ) xin frequency /2 xin frequency /(2 * 256) ( 1 ,1 ) xin frequency /1 xin frequency /(1 * 256) column 19 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - csr csg csb column 20 b7 b6 b5 b4 b3 b2 b1 b0 fsw - - - - fsr fsg fsb fonts designed to be 12x18 display figure 7. 12x18 and 12x16 fonts output display if fss=0; first and last lines omitted
revision 1.0 12/18 28/april/2000 MTV130 myson technology fsr, fsg, fsb - define the color of full screen self-test pattern. ww41, ww40 - determines the shadow width of the window 4 when wshd bit of th window 4 is enabled. please refer to the table 6 for more details. table 6. shadow width setting ww31, ww30 - determines the shadow width of the window 3 when wshd bit of th window 3 is enabled. ww21, ww20 - determines the shadow width of the window 2 when wshd bit of th window 2 is enabled. ww11, ww10 - determines the shadow width of the window 1 when wshd bit of th window 1 is enabled. wh41, wh40 - determines the shadow height of the window 4 when wshd bit of th window 4 is enabled. please refer to the table 7 for more details. table 7. shadow height setting wh31, wh30 - determines the shadow height of the window 3 when wshd bit of th window 3 is enabled. wh21, wh20 - determines the shadow height of the window 2 when wshd bit of th window 2 is enabled. wh11, wh10 - determines the shadow height of the window 1 when wshd bit of th window 1 is enabled. 3.10 color encoder column 21 b7 b6 b5 b4 b3 b2 b1 b0 ww41 ww40 ww31 ww30 ww21 ww20 ww11 ww10 (ww41, ww40) (0, 0) (0, 1) (1, 0) (1, 1) shadow width (unit in pixel) 2 4 6 8 column 22 b7 b6 b5 b4 b3 b2 b1 b0 wh41 wh40 wh31 wh30 wh21 wh20 wh11 wh10 (wh41, wh40) (0, 0) (0, 1) (1, 0) (1, 1) shadow height (unit in line) 2 4 6 8 bordering shadowing m pixels n horizontal lines m pixels n horizontal lines note: m and n are defined by the registers of row 15, column 21 and 22. window area figure 8. character bordering and shadowing and shadowing on window
revision 1.0 13/18 28/april/2000 MTV130 myson technology the encoder generates the video output to rout, gout and bout by integrating window color, border blackedge, luminance output and color selection output (r, g, b) to form the desired video outputs. 3.11 pwm d/a converter there are 4 open-drain pwm d/a outputs (pwm0 to pwm3). these pwm d/a converter outputs pulse width are programmable by writing data to column 23 to 26 registers of row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. and the sampling rate is selected by (pwm1, pwm0) shown as table 5. in applications, all open-drain output pins should be pulled-up by external resistors to supply voltage (5v to 9v) for desired output range. pwmda0 - pwmda3 - define the output pulse width of pin pwm0 to pwm3. column 27 ~ column 31 : reserved. notes : the register located at column 31 of row 15 are reserved for the testing. don?t program this byte anytime in normal operation. row 16 r1, g1, b1 - define the shadow color of window 1. the initial value is (0, 0, 0) after power up. r2, g2, b2 - define the shadow color of window 2. the initial value is (0, 0, 0) after power up. r3, g3, b3 - define the shadow color of window 3. the initial value is (0, 0, 0) after power up. r4, g4, b4 - define the shadow color of window 4. the initial value is (0, 0, 0) after power up. column 23 | column 26 b7 b6 b5 b4 b3 b2 b1 b0 pwmda0 | pwmda3 msb lsb column 0 b7 b6 b5 b4 b3 b2 b1 b0 - r1 g1 b1 - r2 g2 b2 column 1 b7 b6 b5 b4 b3 b2 b1 b0 - r3 g3 b3 - r4 g4 b4 255 0 1 2 3 255 0 1 2 3 m m+1 pwmck pwm0 pwm1 pwm2 pwm3 figure 9. 5 channel pwm output rising edges are separated by one pwmck 4
revision 1.0 14/18 28/april/2000 MTV130 myson technology d2-d0 - these 3 bits define the setup time of hflb to xin and the propagation delay r, g, b, fbkg and int outputs. please refer to figure 12 and table 8. the initial value is (0, 0, 0) after power up. table 8. output and hflb timing to pixel clock column 3 ~ column 31 : reserved. 4.0 absolute maximum ratings dc supply voltage(vdd,vdda) -0.3 to +7 v voltage with respect to ground -0.3 to vdd+0.3 v storage temperature -65 to +150 o c ambient operating temperature 0 to +70 o c 5.0 operating conditions dc supply voltage(vdd,vdda) +4.75 to +5.25 v operating temperature 0 to +70 o c 6.0 electrical characteristics (under operating conditions) column 2 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - d2 d1 d0 symbol (d2, d1, d0) min. typ. max. unit t setup 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns t hold - 500 - - ns t pd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - - - - - - - - 10 11 12 13 14 15 16 17 ns ns ns ns ns ns ns ns symbol parameter conditions (notes) min. max. units v ih input high voltage (pin hflb, vflb, sda, sck, ssb) - 0.7 * vdd vdd+0.3 v
revision 1.0 15/18 28/april/2000 MTV130 myson technology 7.0 switching characteristic (under operating conditions) v il input low voltage (pin hflb, vflb, sda, sck) - vss-0.3 0.3 * vdd v input low voltage (pin ssb) - vss-0.3 0.2 * vdd v v oh output high voltage i oh 3 -5 ma vdd-0.8 - v v ol output low voltage i ol 5 ma - 0.5 v v odh open drain output high volt- age - (for all od pins, and pulled up by external 5 to 9v power supply) 5 9 v v odl open drain output low volt- age 5 ma 3 i dol ( for all od pins ) - 0.5 v i cc operating current pixel rate=150mhz i load = 0ua - 25 ma i sb standby current vin = vdd, i load = 0ua - 12 ma symbol parameter min. typ. max. units f hflb hflb input frequency 15 - 150 khz f vflb vflb input frequency - - 200 hz t r output rise time - 3 - ns t f output fall time - 3 - ns t bcsu ssb to sck set up time 200 - - ns t bch ssb to sck hold time 100 - - ns t dcsu sda to sck set up time 200 - - ns t dch sda to sck hold time 100 - - ns t sckh sck high time 500 - - ns t sckl sck low time 500 - - ns t su:sta start condition setup time 500 - - ns t hd:sta start condition hold time 500 - - ns t su:sto stop condition setup time 500 - - ns t hd:sto stop condition hold time 500 - - ns t setup minimum hflb delay to rising edge of pixel clock tbd - tbd ns t hold minimum pulse width of hflb 25 - - ns t pd propagation delay of output to pixel clock tbd - tbd ns pixin pixel clock input 6 - 150 mhz symbol parameter conditions (notes) min. max. units
revision 1.0 16/18 28/april/2000 MTV130 myson technology 8.0 timing diagrams figure 10. data interface timing(spi) sck ssb sda t sckl t sckh t bcsu t dcsu t dch t bch sck sda t su:sta t sckh t hd:sta t sckl t dcsu t dch t su:sto t hd:sto figure 11. data interface timing(i 2 c) plxin r,g,b, fbkg htone t pd t pd:: propagation delay to r,g,b, fbkg and htone outputs setup t hold t hflb figure 12. output and hflb timing to pixel clock
revision 1.0 17/18 28/april/2000 MTV130 myson technology 9.0 package dimension 9.1 16 pin pdip 300mil 9.2 20 pin pdip 300mil 75 +/-20 90 +/-20 250 +/-4 55 +/-20 90 +/-20 312 +/-12 65 +/-4 55 +/-4 310max 350 +/-20 10 r10max (4x ) 100ty p 18 +/- 2typ 60 +/- 5typ 115 min 750 +/-10 15 min 35 +/-5 7 typ r40 15 max 75 +/-20 90 +/-20 250 +/-4 55 +/-20 90 +/-20 312 +/-12 65 +/-4 55 +/-4 310max 350 +/-20 10 r10max (4x ) 100typ 18 +/-2typ 60 +/-5typ 115 min 1020 +/-10 15 min 35 +/-5 7 typ 15 max r40
revision 1.0 18/18 28/april/2000 MTV130 myson technology 9.3 16 pin sop 300mil 9.4 20 pin sop 300 mil 10.0 characters and symbols pattern please see the attachment. 0.015x45 o 7 o (4x) 0.028 +0.022 /-0.013 0.295 +/-0.004 0.406 +/-0.013 0.406 +/-0.008 0.016 +/-0.004 0.050 0.098 +/-0.006 0.091 (4x) 0.016typ. 0.050typ. 10 1 20 11 0.295+/-0.004inch 0.406+/-0.012inch 0.020x45 0.502+/-0.006inch myson technology usa, inc. http://www.myson.com 20111 stevens creek blvd. #138 cupertino, ca. 95014, u.s.a. tel: 408-252-8788 fax: 408-252-8789 sales@myson.com myson technology, inc. http://www.myson.com.tw no. 2, industry e. rd. iii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5784866 fax: 886-3-5785002

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